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Lattice Semiconductor
Turbo Decoder User’s Guide
Introduction
Lattice’s Turbo Decoder core provides an ideal solution that meets the needs of turbo decoding applications. The
core provides a customizable solution allowing turbo decoding of data in many system designs. This core allows
designers to focus on the application rather than the Turbo Decoder, resulting in a faster time to market.
Turbo coding is an advanced error correction technique widely used in the communications industry. The Turbo
Decoder IP Core from Lattice is compliant with three different standards: 3GPP, 3GPP2 and CCSDS. Lattice’s
Turbo Decoder core was developed in conjunction with Lattice’s Turbo Encoder core to provide a complete solution.
This User’s Guide explains the functionality of the Turbo Decoder core and how it can be implemented to provide
decoding. The Turbo Decoder core comes with the documentation and ?les listed below:
? Lattice gate level netlist
? RTL simulation model
? Core instantiation template
Features
? Fully compatible with Third Generation Partnership Project (3GPP) standard:
– 3GPP TS 25.212 version 4.2.0
? Fully compatible with CDMA2000/3GPP2
– 3GPP2 C.S002-C, May 2002
? Fully compatible with Consultative Committee for Space Data Systems standard:
– CCSDS 101.0-B-5
? Throughput of 2Mbps for 3GPP at 30MHz, 7 iterations, 6-bit input symbol width
? Two’s complement data/parity input
? Depuncturing supported
? Variable soft-widths for input symbols
? User-de?ned number of states
? Variable block sizes during runtime
? Programmable number of iterations (1-15)
? Optional hard decision storage
? Selectable Max-Log-Map or Log-Map algorithm
? Optional external memory with programmable pipeline stages
? Optional double buffering
? Bit Error Rate of 10 -6 (at 1.5 dB Eb/No SNR)
General Description
Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encod-
ers and decoders are key elements in today’s communication systems to achieve the best possible data reception
with fewest possible errors. The basis of turbo coding is to introduce redundancy in the data to be transmitted
through a channel. The redundant data helps to recover original data from the received data. In data transmission,
turbo coding helps achieve near Shannon limit performance.
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相关代理商/技术参数
TURBO-DECO-XP-N1 功能描述:编码器、解码器、复用器和解复用器 Turbo Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
TURBO-ENCO-E2-U3 功能描述:编码器、解码器、复用器和解复用器 Turbo Encoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
TURBO-ENCO-O4-N1 功能描述:编码器、解码器、复用器和解复用器 Turbo Encoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
TURBO-ENCO-P2-U3 功能描述:编码器、解码器、复用器和解复用器 Turbo Encoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
TURBO-ENCO-PM-U3 功能描述:开发软件 Turbo Encoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
TURBO-ENCO-SC-U3 功能描述:编码器、解码器、复用器和解复用器 Turbo Encoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
TURBO-ENCO-X2-U3 功能描述:开发软件 Turbo Encoder RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
TURBO-ENCO-X2-UT3 功能描述:开发软件 TURBO ENCODER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors